`timescale 1ns / 1ps
module maskgen (
  input  [63:0] alu,
  input  [2:0] memdata_width,
  output wire [7:0] rw_wmask
);
reg [7:0] mask;
assign rw_wmask = mask;
integer i;
reg [63:0] offset;
always @(*) begin
    offset = alu % 8;
    case (memdata_width)
        3'b000:  begin
          mask = 8'b00000000;    //不访存
        end
        3'b001: begin            //double word
          mask = 8'b11111111;
        end
        3'b010: begin
          mask = 8'b00001111 << offset;
        end
        3'b011: begin           //half word
          mask = 8'b00000011 << offset;
        end
        3'b100: begin         //byte
          mask = 8'b00000001 << offset;
        end
        3'b101: begin
          mask = 8'b00001111 << offset;    //unsigned word
        end
        3'b110: begin           // unsigned half word
          mask = 8'b00000011 << offset;
        end
        3'b111: begin             //unsigned byte
          mask = 8'b00000001 << offset;
        end
    endcase
end
endmodule